1. Field of the Invention
The present invention relates to a technology for searching data in a computer system and performing a direct-memory-access (DMA) transfer of the data.
2. Description of the Related Art
In recent years, there has been a rapid progress in development of a technology for improving a performance of computer systems. For example, an efficient transfer of data between memories in a computer system and between a memory and an I/O device has been sought after.
A DMA is one of the methods for an efficient transfer of data. In the DMA, instead of a central processing unit (CPU) that performs the data transfer in the computer system, a DMA circuit that is used as a dedicated hardware that performs the data transfer in the computer system based on a command from the CPU.
FIG. 18 is a block diagram of a DMA chip according to a conventional technology. A DMA chip 100 is used in components such as a channel adapter in a disc array unit and includes a memory I/F unit 91 that is connected to a memory (storing a command from a micro processing unit (MPU) in the channel adapter) and a cache I/F unit 97 that is connected to a cache memory (storing data that is searched) on a disc array side.
A registering unit 99 receives instructions (commands) from the MPU in the channel adapter by register writing, provides a memory address and data length etc. as necessary information in a descriptor to a search-data reading unit 92, and provides a cache address and data length etc. as necessary information in the descriptor, to a key-count reading unit 95.
The search-data reading unit 92 reads search data from a comparison-data length from the memory address that is designated to a register and the key-count reading unit 95 reads data of a key unit or a count unit of the comparison-data length from the cache address that is designated to the register. The key-count reading unit 95, when receives search data from the cache memory via the cache I/F unit 97, reads search data from a buffer 93 of the search-data reading unit 92 and compares the respective search data. Then, the key-count reading unit 95 makes a judgment of whether a result of comparison satisfies (Hit) a comparing condition of the search data or not (Miss), as well as interrupts the MPU with each comparison (data search etc.).
FIG. 19 is a sequence diagram of a processing procedure for a data search process according to the conventional technology. The comparison data (comparison key) for performing search of data that is sent from a host computer 101 is stored in a memory 103 of the channel adapter. Data search is started upon setting by register a memory address, a cache address, and a mode etc. to the DMA chip 100 from an MPU 105 in the channel adapter.
The DMA chip 100 receives the search data (comparison key) respectively from the memory 103 and a cache memory 107 on the disc array side, based on the memory address and the cache address that are designated by the MPU 105, and then compares the respective search data.
When a result of comparison of the search data is “Miss”, the DMA chip 100 interrupts the MPU 105. Then, the MPU 105 once again performs register setting in the DMA chip 100 so that the DMA chip 100 performs the next comparison, and performs a key search (comparison of search data). The key search is performed repeatedly till the result of comparison of the search data is “Hit”. When the result of the comparison of the search data becomes “Hit”, the DMA chip 100 interrupts the MPU 105 and stops comparison of data by the DMA chip 100.
Thus, in a search operation by the DMA chip 100, if the comparison of the search data does not match with the comparison condition by comparing once, the MPU 105 is required to give instructions to the DMA chip 100 for the next comparison of the search data.
However, sometimes a transmission speed of a bus (data-transmission path) that receives data from a host computer in the DMA chip differs from a transmission speed of a bus that receives data from the cache memory.
FIG. 20 is a block diagram of a protocol DMA chip according to the conventional technology. A protocol DMA chip 150 has a function of a protocol chip that controls a protocol in a communication with a host computer (not shown) and a function of a DMA chip that includes the DMA circuit.
The protocol DMA chip 150 includes a host (personal computer) I/F unit 156, a protocol control unit 160, a cache I/F unit 157, and a memory I/F 151. The host I/F unit 156 is connected to the host computer. The protocol control unit 160 includes a buffer 161 that stores temporarily search data from the host computer (MPU in the channel adapter). The cache I/F unit 157 is connected to a cache memory on the disc array side.
In the protocol DMA chip 150 shown in FIG. 20, the search data (such as memory address and data length) from the host computer is transmitted to a search-data reading unit 152 without being passed through a registering unit 159. A comparing unit 58 compares search data stored by the search-data reading unit 152 and search data (key) that is transmitted via a key-count reading unit 155 from the cache memory.
In the protocol DMA chip 150, key etc. from the cache memory cannot be read till all the search data stored in the buffer 161 in the protocol control unit 160 is stored in a buffer 153 in the search-data reading unit 152.
While comparing the data, it is necessary that the next transmission (data reception) is performed after a bus with a high transmission-speed of data (such as a peripheral-component-interconnect (PCI) bus that connects the cache I/F unit 157 and the key-count reading unit 155), waits for a processing by a bus with a low transmission-speed of data (such as a bus that connects the protocol control unit 160 and the search-data reading unit 152), which affects an efficiency of data transfer.
An asynchronous file controlling unit that has been disclosed in Japanese Patent Application Laid-open Publication No. H5-165725 performs a cache control by a cache mechanism and an asynchronous file control of a device. The asynchronous file controlling unit includes a buffer for data transfer that stores temporarily transfer data and a comparison circuit that compares the transfer data. A register that can supply from the buffer for data transfer data to the comparing circuit independently apart from a normal route of data transfer is provided. A data transfer to the normal route of data transfer is performed as well during a comparison operation by the comparing circuit.
However, according to the conventional technology, if the comparison of the search data does not match with comparison conditions, the search data cannot be compared by suppressing an overhead of the MPU.